1.Field of Invention
The present invention pertains to the field of processors. More particularly, this invention relates to a processor having a cache of memory segment descriptors.
2.Art Background
Prior computer systems typically contain one or more processors along with other hardware subsystems such as memory and specialized peripheral hardware. Such processors commonly communicate with memory and peripheral hardware via an address bus and a corresponding data bus. Typically, individual memory locations are selected by addresses transferred via the address bus. The range of address selection available to such a processor may be referred to as the memory address space of the processor.
Some processors employ a segmented model of such a memory address space. For example, one type of processor having a segmented memory model may be referred to as an X86 processor or a processor that conforms to the X86 architecture. The native instruction code for such an X86 type of processor typically represents memory addresses as 16 bit values which may be referred to as logical addresses. On the other hand, later generations of the X86 architecture include a 32 bit memory address space. Such later generation X86 processors are capable of generating 32 bit physical addresses which may be referred to as linear addresses.
Typically, the memory address space for such an X86 processor is logically subdivided into a set of segments each having a 16 bit logical address range. Such an X86 processor usually contains a set of internal segment registers that contain segment descriptors. Each segment descriptor typically includes a 32 bit base address which is used by the processor to convert 16 bit logical addresses into 32 bit physical addresses. Each segment descriptor also usually includes segment limit values and a variety of attribute flags for the corresponding segment.
Typically, such an X86 processor maintains segment descriptors in a set segment descriptor tables located in an external memory. Such a processor usually reloads the internal segment registers under a variety of conditions as required by the operating system, the application programs, and other software elements of the system.
In addition, such an X86 processor commonly includes an internal data cache that reflects selected portions of external memory. Such an internal data cache typically enhances performance by providing low latency access to data stored in the internal data cache during load memory and store memory operations. Such an internal data cache may also be referred to as an L1 data cache. Prior X86 processors typically cache segment descriptors with other types of data in such an internal data cache.
Typically, the caching strategy for such an internal data cache is selected to optimize access to the types of data most often encountered by the processor. For example, such internal data caches are usually managed such that the data for the memory locations most recently accessed by the processor remain in the cache while the data for memory locations least recently accessed are evicted from the cache to external memory.
Unfortunately, such a caching strategy is typically not well suited for caching segment descriptors. For example, the rate of occurrence of load memory operations targeted for the segment descriptor tables is usually lower than the rate for other types of cached data. As a consequence, the segment descriptor targeted by a particular load memory operation is typically evicted from the data cache before the next load memory operation for that segment descriptor occurs. Therefore, such load memory operations targeted for segment descriptors typically miss the data cache and require an access to the segment tables located in the external memory.
Moreover, such an external memory access is typically much slower than an access to the internal data cache. Such high latency accesses to external memory typically slows the overall speed of such a processor during memory operations that require access to segment descriptors. In addition, such segment descriptors unnecessarily consume space in the data cache of prior processors while not providing the benefits normally associated with data caching.